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Principal Engineer, ASIC Design Verification Location: Bangalore (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the worlds leading semiconductor ecosystem, Ayar Labs co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next-generation silicon photonic chip. In this role, you will serve as a technical lead, architecting scalable verification environments and driving high-quality silicon from concept to tape-out. You will look beyond block-level testing to solve complex system-level challenges, define methodologies, and mentor a growing team of bright engineers. Essential Functions: - Architect Testbenches: Define and build modular, reusable, and scalable UVM testbench architectures for complex IP blocks and Sub-systems. - Drive Methodology: Set the standard for verification methodologies, coding guidelines, and coverage metrics. Evaluate and deploy new EDA tools, formal verification techniques, or emulation flows. - Strategic Planning: Collaborate with Architects and RTL Designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro-architecture testability. - Complex Debugging: Lead the effort to debug elusive hardware bugs, root-causing issues across RTL, firmware, and the verification environment. - Technical Leadership: Mentor senior and junior engineers, conduct code reviews, and foster a culture of engineering excellence. - Automation & Efficiency: Develop scripts and infrastructure to automate regression testing, performance analysis, and coverage closure. Basic Qualifications: - Experience: MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience in ASIC/SoC verification. - Core Competency: Expert-level proficiency in SystemVerilog and UVM (Universal Verification Methodology). - Architecture: Proven track record of building verification environments from scratch (Agents, Scoreboards, Sequencers, etc.). - Protocols: Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe). - Scripting: Robust proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell). - Coverage: Experience defining functional coverage groups and driving logic verification to 100% closure. Preferred Qualifications: - Formal Verification: Experience with formal property checking (VC Formal) and writing SVA (SystemVerilog Assertions). - Emulation & Acceleration: Hands-on experience with hardware emulation platforms. - Processor Knowledge: Familiarity with RISC-V or ARM architecture and coherency protocols. - Mixed Signal: Experience in Analog/Mixed-Signal (AMS) verification. - Modeling: Experience with C/C++ or SystemC modeling for reference models. - Experience working on digital designs with multiple clock domains and clock dividers - Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment - Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends - Experience with verification of HBM memory interfaces (PHY and controller) - Experience in formal model equivalence checking tools and verification methodology - Programming experience in Python NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please dont send candidates to Ayar Labs, and do not contact our managers. .
Here's how to pick the right one and stand out in your application.
144.883Jobs
31.687IN
81%EN
That number is real. WorkMundi's database shows 144,883 open engineer roles across the world. India has the most with 31,687 jobs, followed by the United States with 30,084. If you just finished reading one job ad and felt paralyzed by choice, you're not alone—but this scale is actually an advantage. It means you can afford to be selective.
Start by geography and language. The majority of engineer ads—117,837 of them—have the job posting text written in English. Use that as one filter, but remember: the ad text language tells you nothing about whether the role actually requires you to speak English day-to-day. Read the job description carefully. Then check which countries have the volume you're targeting. Singapore, Poland, and Australia round out the top five after India and the US.
Next, learn who's hiring. Accenture has posted 2,801 engineer roles. andurilindustries, speechify, and jobgether are also actively recruiting. If you're applying to one of these names, research their hiring patterns and interview style before you apply. That homework pays off.
When you interview, expect the question every engineer hears: 'Tell me about a time you had to debug a problem that wasn't in your job description.' Have a specific story ready—not a general one. Name the tools, the deadline pressure, and what you learned. Hiring managers listen for whether you see problem-solving as part of the role itself, not a favour.