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Staff Memory Design EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You AreYou have spent years in the analog and mixed-signal trenches, designing memory circuits that have to work across voltage corners, temperature extremes, and process variations without a second chance. You know that an SRAM bitcell is not just six transistors on a page, it is a tradeoff between read stability, write margin, leakage, and area, and you have made those calls enough times to know which knob to turn when a design is not closing. You think in terms of transistor-level behavior, not just simulation results. When a memory fails at a corner, you do not just re-run SPICE, you go back to the schematic, check your layout parasitics, and figure out what actually broke. You have worked closely with layout teams, and you understand that a good floorplan saves you three weeks of iteration later. You are comfortable owning a memory block from architecture through tapeout. You can sit with a compiler team and explain why your bitcell needs a specific routing constraint, then turn around and review a layout with a physical design engineer without losing context. At Synopsys, you will design embedded memories that ship in our IP portfolio and power chips across the industry. What You'll Be DoingDesign and develop embedded CMOS memories including single-port SRAM, dual-port SRAM, register files, and ROM for Synopsys IP productsOwn circuit architecture and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurationsPerform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verificationDevelop and verify bitcells, define layout rules, and drive layout design and parasitic extraction closure with the physical design teamInterface with CAD teams to integrate memory designs into compiler automation flows and generate EDA models for customer useCollaborate with frontend engineers to define and validate full verification flows including timing, power, and functional modelsMentor junior engineers and lead technical aspects of memory design projects from concept to deliveryThe Impact You Will HaveYour memory designs will ship as part of Synopsys IP offerings used by semiconductor companies worldwide in high-volume production chipsThe bitcells and architectures you develop will define performance, power, and area benchmarks for next-generation embedded memory IPYour layout planning and verification rigor will reduce tapeout risk and speed time to market for memory compiler releasesThe automation flows you help define will enable faster, more reliable memory generation for customers across process nodesYour technical mentorship will build design capability within the team and raise the quality bar for future memory productsThe tradeoffs you make between speed, power, and density will directly influence customer adoption and competitiveness in the IP marketYour collaboration with CAD and frontend teams will improve tooling, models, and verification coverage across the memory IP portfolioWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics, or a related technical fieldDeep hands-on experience with CMOS memory circuit design including SRAM, register files, or ROMProficiency with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based simulatorsStrong understanding of memory layout design, parasitic extraction, and layout verification tools like Calibre or AssuraScripting capability in C-Shell, Perl, or similar languages; experience with C++ or JavaScript is a plus .
Here's how to pick the right one and stand out in your application.
144.883Jobs
31.687IN
81%EN
That number is real. WorkMundi's database shows 144,883 open engineer roles across the world. India has the most with 31,687 jobs, followed by the United States with 30,084. If you just finished reading one job ad and felt paralyzed by choice, you're not alone—but this scale is actually an advantage. It means you can afford to be selective.
Start by geography and language. The majority of engineer ads—117,837 of them—have the job posting text written in English. Use that as one filter, but remember: the ad text language tells you nothing about whether the role actually requires you to speak English day-to-day. Read the job description carefully. Then check which countries have the volume you're targeting. Singapore, Poland, and Australia round out the top five after India and the US.
Next, learn who's hiring. Accenture has posted 2,801 engineer roles. andurilindustries, speechify, and jobgether are also actively recruiting. If you're applying to one of these names, research their hiring patterns and interview style before you apply. That homework pays off.
When you interview, expect the question every engineer hears: 'Tell me about a time you had to debug a problem that wasn't in your job description.' Have a specific story ready—not a general one. Name the tools, the deadline pressure, and what you learned. Hiring managers listen for whether you see problem-solving as part of the role itself, not a favour.