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Design Verification Engineer Experience- 815 Years Freshers are not eligible for this position. Company Description Core ASIC Inc. is a customer-focused VLSI design and verification services company with operating entities in Bangalore, India and Austin, Texas. The company delivers complete spec-to-silicon turnkey solutions, including firmware co-development, for semiconductor and IoT applications. Its silicon-proven platform solutions support custom semiconductor development across IP design and verification, VIP development, SoC verification, and emulation services. Core ASIC emphasizes on-time delivery, strong client alignment, and a product development approach that balances technology, time-to-market, and ROI. Supported by experienced engineering and technology teams, the company positions itself as a growth partner to its clients rather than a traditional vendor. Qualifications: Good proficiency in System Verilog and UVM .Hands-on expertise in any of the following protocols is preferred: PCIe, DDR, Ethernet, CXL, or USB.Excellent debugging and problem-solving skills.Understanding of computer architecture, including processor microarchitecture, bus protocols, and memory systems.Experience with scripting languages such as Python or Perl.Familiarity with Cadence Xcelium/Incisive,Synopsys VCS and Siemens QuestaSim.Knowledge of formal verification, or emulation is an added advantage.Good written and verbal communication skills, with ability to work as individually and collaboratively in a team environment.Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline. Role & responsibilities: Develop and execute comprehensive verification plans.Build reusable UVM-based verification environments.Create constrained-random test cases, assertions, scoreboards, and functional coverage.Debug RTL and verification issues using waveform viewers and debuggers.Work closely with design, architecture, and software teams to ensure project success.Drive coverage closure and verification sign-off.Mentor junior verification engineers, providing technical guidance, code reviews, and bestpractice recommendations .