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Position: DFT Lead Engineer Cluster Model Experience: 6+ Years Location: Bangalore About the Role We are looking for an experienced DFT Lead Engineer to join its semiconductor engineering team. The role will be responsible for leading and driving Design for Testability (DFT) activities for complex ASIC/SoC designs under a Cluster Model. The ideal candidate should have strong hands-on experience in DFT architecture, implementation, verification and sign-off, along with the ability to work closely with RTL, Physical Design, Verification, STA and other cross-functional engineering teams. The candidate will be expected to take ownership of DFT activities, drive technical execution, resolve complex DFT issues and provide technical guidance to team members. Key Responsibilities DFT Architecture && Planning Define and implement DFT architecture for complex ASIC/SoC designs. Develop DFT strategies based on product and test requirements. Work on scan architecture, test compression, ATPG, MBIST, LBIST and other DFT methodologies. Evaluate DFT requirements and ensure testability targets are achieved. Participate in DFT planning, design reviews and technical discussions. DFT Implementation Drive end-to-end DFT implementation from RTL through physical design and tape-out. Implement and integrate scan chains, test compression logic, test modes and other DFT structures. Work with ATPG tools to generate and analyze test patterns. Perform scan insertion, DFT rule checking and DFT verification. Analyze and resolve DFT-related implementation issues. Analyze test pattern quality, testability and pattern-related issues. Work with verification and design teams to resolve ATPG/DFT violations. MBIST / Memory Test Work on MBIST architecture and implementation for embedded memories. Configure and validate MBIST controllers and associated test logic. Debug MBIST failures and memory test coverage issues. Coordinate with memory and design teams for MBIST integration and validation. JTAG / Boundary Scan Work on JTAG and IEEE 1149.x-based test architectures. Implement and validate boundary scan and related test structures. Debug JTAG/test access-related issues. Support integration and validation of test access mechanisms. DFT Verification && Sign-Off. Support gate-level simulation and pattern validation. Work closely with Physical Design teams to resolve scan-chain and physical implementation issues. Support DFT sign-off activities before tape-out. Cluster Model Responsibilities Take ownership of DFT activities for the assigned design cluster. Coordinate DFT execution across multiple design blocks. Ensure consistency of DFT methodology across the cluster. Track DFT deliverables, issues, dependencies and schedules. Coordinate with RTL, Physical Design, Verification, STA and other engineering teams. Provide technical leadership and mentorship to junior DFT engineers. Participate in technical reviews and contribute to improving DFT methodologies and processes. Cross-Functional Collaboration The candidate will work closely with: RTL Design Engineers Physical Design Engineers Design Verification Engineers STA Engineers Silicon Validation Teams Product/Test Engineering Teams DFT and CAD teams Project and Technical Leads Required Technical Skill Knowledge of MBIST and memory test methodologies. Knowledge of JTAG / Boundary Scan. Understanding of scan compression and test modes. Experience working through RTL-to-GDS/tape-out DFT flow. Strong understanding of ASIC design and semiconductor development processes. Experience handling multiple IPs/blocks in a cluster-based development model. Experience with DFT-related EDA tools such as Synopsys, Cadence or Siemens EDA/Mentor tools. Experience with DFT sign-off and tape-out activities. Knowledge of physical DFT implementation and scan-chain optimization. Scripting/programming knowledge in TCL, Perl, Python or Shell is an advantage. Prior experience leading or mentoring DFT engineers will be preferred. Leadership && Behavioral Competencies Strong analytical and problem-solving ability. Ability to independently debug complex DFT issues. Strong ownership and accountability for deliverables. Ability to lead technical discussions and drive issues to closure. Strong collaboration skills across multiple engineering functions. Ability to mentor and guide junior engineers. Education B.E./B.Tech/M.E./M.Tech in Electronics && Communication Engineering, Electrical Engineering, VLSI, Microelectronics or a related discipline. Candidate Profile The ideal candidate should be a hands-on DFT professional who can independently manage DFT activities for an assigned cluster while working effectively with multiple engineering teams. Candidates with experience in ASIC/SoC DFT, ATPG, Scan, MBIST, JTAG, DFT verification and sign- off will be strongly preferred. Compensation && Joining CTC:25 LPA, flexible for suitable candidates Notice Period: Immediate Joiners / Short Notice Candidates Preferred
Here's how to pick the right one and stand out in your application.
144.883Jobs
31.687IN
81%EN
That number is real. WorkMundi's database shows 144,883 open engineer roles across the world. India has the most with 31,687 jobs, followed by the United States with 30,084. If you just finished reading one job ad and felt paralyzed by choice, you're not alone—but this scale is actually an advantage. It means you can afford to be selective.
Start by geography and language. The majority of engineer ads—117,837 of them—have the job posting text written in English. Use that as one filter, but remember: the ad text language tells you nothing about whether the role actually requires you to speak English day-to-day. Read the job description carefully. Then check which countries have the volume you're targeting. Singapore, Poland, and Australia round out the top five after India and the US.
Next, learn who's hiring. Accenture has posted 2,801 engineer roles. andurilindustries, speechify, and jobgether are also actively recruiting. If you're applying to one of these names, research their hiring patterns and interview style before you apply. That homework pays off.
When you interview, expect the question every engineer hears: 'Tell me about a time you had to debug a problem that wasn't in your job description.' Have a specific story ready—not a general one. Name the tools, the deadline pressure, and what you learned. Hiring managers listen for whether you see problem-solving as part of the role itself, not a favour.