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Experience- 12+ years Location: Bangalore Key Responsibilities- End-to-end PnR floorplan to GDS handoff on advanced FinFET nodes.Timing closure with AOCV / POCV across PVT corners; late-stage ECO management.Physical sign-off: DRC, LVS, ERC, power integrity (IR drop / EM).Low-power implementation: multi-voltage, power gating, retention, DVFS.Lead & mentor 515 backend engineers through tape-out milestones.Primary technical interface with client program teams. Must have: 12+ years backend physical design; tapeout ownership at 16 nm or below. Innovus or ICC2 for PnR; PrimeTime or Tempus for STA Calibre DRC / LVS sign-off and foundry rule resolution Tcl scripting for flow automation; Python a strong plusProcess nodes: TSMC 5 nmTSMC 7 nmTSMC 12 nmTSMC 16 nm Samsung 4 nm GF 12 nm GF 22FDXTSMC 22 nm.Tools : P&R Cadence Innovus, Synopsys ICC2 STA PrimeTime, Tempus Phys Ver Mentor Calibre DRC / LVS / ERC Synthesis Genus, Fusion Compiler Power Voltus, Power Artist CPF / UPF Scripting Tcl, Python, Bash.Good communication skills. .