Analog / Mixed-Signal Circuit Design Enginee

Key Responsibilities Circuit Design & Architecture Develop transistor-level circuit designs for analog/mixed-signal macros across advanced CMOS process nodes (28nm, 16nm FinFET, 7nm, and below) Architect and implement LDO regulators, bandgap references, and POR circuits with precision bias networks meeting tight temperature, supply, and process variation targets Design high-speed receiver (RX) front-ends, clock-data recovery (CDR) loops, DLL, and PLL circuits targeting multi-Gbps serial interface standards Implement transmitter (TX) drivers with programmable swing, pre-emphasis, and equalization for PCIe, USB, MIPI, DDR, and custom SerDes links Design DC-DC switching converters, charge pumps, and analog switch circuits optimized for efficiency, area, and EMI compliance Develop oscillator circuits (ring, relaxation, LC) and clocking distribution networks meeting phase noise, jitter, and duty-cycle specifications Design under-voltage and over-voltage protection circuits including supervisory functions, brown-out detection, and soft-start control Create bias generator networks, current references, and common-mode feedback circuits supporting system-level analog infrastructure Simulation & Verification Perform comprehensive SPICE-level simulations (DC, AC, transient, noise, Monte Carlo, and corner analysis) using Cadence Spectre, HSPICE, or equivalent Conduct behavioral modeling in Verilog-A / Verilog-AMS to enable system-level mixed-signal co-simulation Execute process, voltage, and temperature (PVT) corner verification to guarantee robust, first-time silicon success Perform post-layout simulation with extracted parasitics (RC/RLC) and validate performance degradation vs. schematic targets Collaborate with physical design/layout engineers to review parasitic impact and guide layout techniques (shielding, symmetry, matching) Generate and maintain comprehensive simulation decks and regression test benches for IP re-use and future node porting Specification, Documentation & Review Author detailed circuit design specifications, schematic documentation, and simulation result reports Participate in and lead design reviews, peer reviews, and architectural trade-off analyses Interface with system architects and SoC integration teams to define block-level requirements and pin specifications Support IP characterization, datasheet generation, and application note creation Silicon Validation & Bring-Up Develop bench test plans and support silicon bring-up and characterization of first-pass prototypes Analyze measured silicon data vs. simulation predictions, identify failure modes, and drive root-cause analysis Propose and implement design fixes and revision updates based on silicon findings Work with test engineering teams to develop automated production test solutions (ATE) for manufactured silicon Collaboration & Mentorship Work in close partnership with layout engineers, DFT engineers, and SoC integration teams throughout the full design cycle Mentor junior circuit designers and contribute to engineering capability building within the team Participate in foundry interactions, PDK evaluations, and device model reviews Required Qualifications Bachelor of Science in Electrical Engineering (BSEE) Mandatory Minimum 3 years of professional experience in analog/mixed-signal IC circuit design Proficiency with Cadence Virtuoso Schematic Editor and Analog Design Environment (ADE-L/XL/GXL) Hands-on SPICE simulation experience using Spectre, HSPICE, or Eldo including Monte Carlo and PVT corner analysis Demonstrated design experience with at least 3 of the macro categories listed in the Circuit Design Scope section Solid understanding of MOSFET device physics, noise analysis, stability (phase margin), and mismatch/variation effects Familiarity with FinFET or advanced CMOS process node design constraints and device models Knowledge of analog design fundamentals: op-amp topologies, feedback theory, frequency compensation, and bandgap references Preferred Qualifications Experience with high-speed serial interface standards: PCIe Gen 4/5, USB 3.x/4, DDR5, MIPI, or custom SerDes at 10112 Gbps Proficiency in Verilog-A / Verilog-AMS behavioral modeling for system-level mixed-signal simulation Prior collaboration with foundries such as TSMC, Samsung, GlobalFoundries, or Intel Foundry