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SoC Floorplan Lead - Principal Engineer / Senior Staff www.EnchargeAi.com The 10 Hottest Semiconductor Startups Of 2025 (So Far) https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-far page=11 https://www.enchargeai.com/blog/the-efficiency-imperative-energy-will-define-ais-next-chapter The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities - Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). - Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. - Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. - Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. - Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. - Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. - Methodology Development: Build and maintain scalable Floorplanning workflows and scripts (Tcl, Python) tailored for a lean, quick-moving start-up team. Required Skills & Qualifications - Experience: 12 -20 years years of hands-on experience in Physical Design SoC Floor planning preferably in Datacenter domain , with at least 3 years acting as a lead or primary owner of SoC-level Floorplanning. - Domain Expertise: Proven track record of taping out large, complex chipsspecifically for Data Center, Networking, or AI/Machine Learning applications. - Start-Up Mentality: Highly driven, self-motivated, and comfortable with ambiguity. You take extreme ownership of your domain, pivot quickly when needed, and roll up your sleeves to get things done. - Technical Depth: - Deep understanding of how RTL structures and architectural decisions impact physical design PPA. - Extensive experience with bump planning, flip-chip package requirements, and die-to-package co-optimization. - Strong knowledge of analog/mixed-signal IP integration, shielding, and custom routing constraints. - Expertise with industry-standard physical design tools ( Cadence Innovus). - Education: BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. Preferred Qualifications - Experience with multi-die / chiplet integration (2.5D, 3D packaging, interposers, UCIe). - Strong scripting and automation skills (Tcl, Python, Perl, Makefile). - Knowledge of advanced clocking architectures (H-trees, meshes) for highly synchronous AI fabrics. What We Offer - Impact: The opportunity to build ground-up architecture and see your ideas taped out in cutting-edge silicon. - Equity: Competitive start-up equity packageswhen the company wins, you win. - Culture: A flat, collaborative, and bureaucracy-free environment surrounded by top-tier industry veterans. Skills 2.5D 3D UCIe Tcl Python Perl Makefile Innovus (Cadence ) Bump PPA SoC Floorplanning Datacenter Networking AI ML DL Full-chip AMS Serdes PCIe Ethernet DDR7 LPDDR5 Voltus Redhawk Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com www.mulyatech.com .
Here's how to pick the right one and stand out in your application.
144.883Jobs
31.687IN
81%EN
That number is real. WorkMundi's database shows 144,883 open engineer roles across the world. India has the most with 31,687 jobs, followed by the United States with 30,084. If you just finished reading one job ad and felt paralyzed by choice, you're not alone—but this scale is actually an advantage. It means you can afford to be selective.
Start by geography and language. The majority of engineer ads—117,837 of them—have the job posting text written in English. Use that as one filter, but remember: the ad text language tells you nothing about whether the role actually requires you to speak English day-to-day. Read the job description carefully. Then check which countries have the volume you're targeting. Singapore, Poland, and Australia round out the top five after India and the US.
Next, learn who's hiring. Accenture has posted 2,801 engineer roles. andurilindustries, speechify, and jobgether are also actively recruiting. If you're applying to one of these names, research their hiring patterns and interview style before you apply. That homework pays off.
When you interview, expect the question every engineer hears: 'Tell me about a time you had to debug a problem that wasn't in your job description.' Have a specific story ready—not a general one. Name the tools, the deadline pressure, and what you learned. Hiring managers listen for whether you see problem-solving as part of the role itself, not a favour.