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Job Title: Senior PD engineer : Synthesis & STA Location: Bangalore INDIA Hybrid / Remote Role Overview We are seeking a highly skilled VLSI Synthesis & STA Specialist to take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips. In this role, you will act as a critical bridge between the front-end design and back-end physical implementation teams. You will not only drive synthesis execution to meet aggressive target frequencies but also act as an advisor to the RTL team, providing structural feedback to optimize the netlist. This role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence. Key Responsibilities Synthesis Ownership: Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics. Quality Signoff: Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff. RTL Collaboration: Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff. Frequency & LOL Optimization: Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements. Micro-architecture Guidance: Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist. Role Expansion: Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence. Required Skills & Qualifications Experience: 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis. EDA Tools Expertise: Hands-on experience with industry-standard synthesis tools, with a strong preference for Cadence Genus . Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required. Timing & STA: Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis. RTL & Logic Fundamentals: Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools. Netlist Optimization: Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth. Scripting/Automation: Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts. Cross-Functional Communication: Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams. Preferred Qualifications Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion. Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality). Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.
Here's how to pick the right one and stand out in your application.
144.883Jobs
31.687IN
81%EN
That number is real. WorkMundi's database shows 144,883 open engineer roles across the world. India has the most with 31,687 jobs, followed by the United States with 30,084. If you just finished reading one job ad and felt paralyzed by choice, you're not alone—but this scale is actually an advantage. It means you can afford to be selective.
Start by geography and language. The majority of engineer ads—117,837 of them—have the job posting text written in English. Use that as one filter, but remember: the ad text language tells you nothing about whether the role actually requires you to speak English day-to-day. Read the job description carefully. Then check which countries have the volume you're targeting. Singapore, Poland, and Australia round out the top five after India and the US.
Next, learn who's hiring. Accenture has posted 2,801 engineer roles. andurilindustries, speechify, and jobgether are also actively recruiting. If you're applying to one of these names, research their hiring patterns and interview style before you apply. That homework pays off.
When you interview, expect the question every engineer hears: 'Tell me about a time you had to debug a problem that wasn't in your job description.' Have a specific story ready—not a general one. Name the tools, the deadline pressure, and what you learned. Hiring managers listen for whether you see problem-solving as part of the role itself, not a favour.